1. Technical Field
The present invention relates to a non-volatile memory device and a method of fabricating the same, and more particularly, to a non-volatile memory device, which is capable of writing and reading data by a switching operation of a conductive metal line, and a method of fabricating the same.
2. Discussion of Related Art
Generally, memory devices used for storing data can be classified as volatile memory devices and non-volatile memory devices. Among volatile memory devices, typical memory device types include, for example, a dynamic random access memory (DRAM) or a static random access memory (SRAM). Volatile memory devices are fast in operating speed, for example in inputting and outputting of data, but such devices do not retain stored data when the power supply is removed. Typical non-volatile semiconductor memory device types include, for example, an erasable programmable read only memory (EPROM) or an electrically erasable programmable read only memory (EEPROM). Non-volatile semiconductor memory devices are relatively slow in operation speed, for example in the inputting and outputting of data, but such devices retain stored data when the power supply is discontinued.
Conventional memory devices have been fabricated through the use of metal oxide semiconductor field effect transistors (MOSFET) that are based on metal oxide semiconductor (MOS) technology. For example, stacked-gate type transistor memory devices and trench-gate type transistor memory devices are popular, and advancements on these technology forms have been under development for many years. The stacked gate type transistor memory device includes a gate structure that is stacked on a semiconductor substrate composed of silicon material. The trench gate type transistor memory device includes a gate structure that is embedded in the semiconductor substrate. However, to prevent a short channel effect in a MOSFET device, the width and length of a channel need to be more than a predetermined length, and the thickness of a gate insulating layer, which is formed between a gate electrode positioned at an upper end of the channel and a semiconductor substrate, needs to be extremely thin. Due to these basic limitations, further advancements in MOSFET technology have faced extreme difficulty, especially in nanoscaled structures. Moreover, since a high-temperature process is required for the technology of depositing single-crystalline silicon, which is used as a channel layer under the gate electrode, on a thin film, it is common for the transistor positioned thereunder to become deteriorated, and thus, the stacking process for fabricating the MOSFET is difficult.
In view of the above, research is being actively conducted to develop a memory device having a structure that is an alternative to the MOSFET. In recent years, micro-electro-mechanical system (MEMS) technology and nano-electro-mechanical system (NEMS) technology, which have been developed by applying semiconductor technology, have become influential. Among these, a memory device using a carbon nanotube structure is disclosed in US Patent Publication No. 2004/0181630 entitled “Devices having horizontally-disposed nanofabric articles and methods of making the same,” incorporated herein by reference.
A conventional memory device in accordance with the above carbon nanotube structure will now be described with reference to FIG. 1, which is a sectional view illustrating a conventional memory device.
As illustrated in FIG. 1, the conventional memory device comprises: a lower electrode 112 and an upper electrode 168 which are spaced apart from each other at a predetermined interval and are parallel in one direction; and a nanotube patch 154 which is spaced away from the lower electrode 112 and the upper electrode 168 and which is configured to deflect between lower and upper electrodes 112, 168, and which stores predetermined data depending on its position being spaced apart from or in contact with, the lower electrode 112 or upper electrode 168.
The lower electrode 112 is embedded in a cavity formed in a first interlayer insulating layer 176 on a semiconductor substrate. For example, the lower electrode 112 is made of conductive metal or semiconductor materials.
The upper electrode 168 is configured to be spaced apart from the lower electrode 112 in a position suspended above the lower electrode 112. The upper electrode 168 is formed to be supported by a second interlayer insulating layer (not shown) that is formed on the first interlayer insulating layer 176.
The nanotube patch 154 is positioned in a center portion of the gap 174 formed between the lower electrode 112 and the upper electrode 168, and can be made to be in contact with the lower electrode 112 or the upper electrode 168, depending on predetermined conditions. For example, the nanotube patch 154 can be anchored on a nitride layer formed on the first interlayer insulating layer 176 at both side edges of the lower electrode 112, so that it is suspended above the lower electrode 112 by a predetermined height. Further, the nanotube patch 154 can deflect to make contact with the lower electrode 112 or the upper electrode 168 to which an electric charge opposite that of an electric charge applied to the nanotube patch 154 is applied. When the nanotube patch 154 comes into contact with the lower electrode 112, the same electric charge as that applied to the nanotube patch 154 is applied to the upper electrode 168 being parallel to the lower electrode 112. In order for the nanotube patch 154 to remain in contact with the lower electrode 112, a sufficient electric charge must be applied to the lower electrode 112. When the nanotube patch 154 comes into contact with the upper electrode 168, the opposite electric charge to that applied to the nanotube patch 154 is applied to the upper electrode 168, and the same electric charge as that applied to the nanotube patch 154 is applied to the lower electrode 112.
Accordingly, the conventional memory device described above can store one bit of data, the state of the bit corresponding to the state, or position, of the nanotube patch 154 in the gap between the lower electrode 112 and the upper electrode 168; that is, whether the nanotube patch is in a position in contact with the lower electrode 112 or upper electrode 168, respectively, or whether the nanotube patch is in a suspended state in the gap, 174, not in contact with either of the lower electrode 112 or upper electrode 168.
However, the conventional memory device described above has the following problems.
First, in the conventional memory device, to maintain the state that the nanotube patch 154 is in contact with the lower electrode 112 or upper electrode 168, a predetermined electric charge must be continuously supplied to the nanotube patch 154 and the lower electrode 112 or upper electrode 168 being in contact with the nanotube patch 154, thereby increasing standby power consumption. When the electric charge supply is discontinued, the nanotube patch will recover to its original state, and any written information corresponding to the position of the nanotube patch 154 is lost; therefore, a non-volatile memory device cannot be realized using this technology.
Second, in the conventional memory device, when the nanotube patch 154 in contact with the lower electrode 112 or upper electrode 168 needs to be separated therefrom, a van der Waal's force is operable between the patch 154 and the lower electrode 112 or upper electrode 168 which is made of a conductive metal material. Accordingly, the nanotube patch 154 is not always separated from the lower electrode 112 or upper electrode 168 and thus, writing of information cannot be clearly performed, thereby deteriorating reliability of the memory device.